EDN

Get a hands-on tutorial in FPGA design at ESC Silicon Valley

I just heard from my chum Jason Pecor at Alorium Technology. Jason and his colleague, Bryan Craker, will be giving a 2-hour tutorial at ESC Silicon Valley 2016. Titled A Novel Hands-On Approach to ...
Design-Reuse

Avery Design Systems Announces SimAccel FPGA Accelerator

TEWKSBURY, MA., --August 5, 2019 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of the SimAccel FPGA-based accelerator to ...
Semiconductor Engineering

Scaling Open-Source HW Accelerator for Deep NN Inference (UDE, Fraunhofer IMS)

Researchers from University of Duisburg-Essen and Fraunhofer Institute for Microelectronic Circuits and Systems have ...
EDN

Tutorial: Designing an FPGA from scratch – It’s like déjà vu all over again!

Where does the time go? About four years ago as I pen these words, I was introduced to expert Swedish ASIC designer Sven-Åke Andersson. At that time, Sven was aware that, with their increasing NRE ...
New Electronics

AMD unveils FPGA-based accelerator for ultra efficient electronic trading

AMD has unveiled its new Alveo UL3524 accelerator card, a fintech accelerator that’s been designed for ultra-low latency electronic trading applications. Already deployed by a number of trading firms, ...
Design-Reuse

CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem

WOODCLIFF LAKE, NJ USA, Oct. 17, 2017 – A hardware accelerator that addresses the data compression and storage optimization needs of performance-critical data center applications is now available from ...